Browsing by Author "Riem, Joseph"

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Explainable Learning-Based Intrusion Detection Supported by Memristors
(IEEE, 2023) Chen, Jingdi ; Zhang, Lei ; Riem, Joseph ; Adam, Gina ; Bastian, Nathaniel D. ; Lan, Tian
Deep learning based methods have demonstrated great success in network intrusion detection. However, the use of Deep Neural Networks (DNNs) makes it difficult to support real-time, packet-level detections in communication networks that handle high-speed traffic with low latency and energy. To this end, this paper proposes a novel approach to efficiently realize a DNN-based classifier by converting it into a pruned, explainable decision tree and evaluating its hardware implementation using an emerging architecture based on memristor devices, in order to support network intrusion detections on the fly. Preliminary experiments on real-world datasets show that the proposed method achieves nearly four orders of magnitude speed up while retaining the desired accuracy.
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RIDE: Real-time Intrusion Detection via Explainable Machine Learning Implemented in a Memristor Hardware Architecture
(IEEE, 2023-11-07) Chen, Jingdi; Zhang, Lei; Riem, Joseph; Adam, Gina; Bastian, Nathaniel D.; Lan, Tian
Deep Learning (DL) based methods have shown great promise in network intrusion detection by identifying malicious network traffic behavior patterns with high accuracy, but their applications to real-time, packet-level detections in highspeed communication networks are challenging due to the high computation time and resource requirements of Deep Neural Networks (DNNs), as well as lack of explainability. To this end, we propose a packet-level network intrusion detection solution that makes novel use of Recurrent Autoencoders to integrate an arbitrary-length sequence of packets into a more compact joint feature embedding, which is fed into a DNN-based classifier. To enable explainability and support real-time detections at micro-second speed, we further develop a Software-Hardware Co-Design approach to efficiently realize the proposed solution by converting the learned detection policies into decision trees and implementing them using an emerging architecture based on memristor devices. By jointly optimizing associated software and hardware constraints, we show that our approach leads to an extremely efficient, real-time solution with high detection accuracy at the packet level. Evaluation results on real-world datasets (e.g., UNSW and CIC-IDS datasets) demonstrate nearly three-nines detection accuracy with a substantial speedup of nearly four orders of magnitude.